In a typical processing system there is an oscillator which generates a master clock for operating all the circuits within that system. The clocks which operate the system are all generated from the same master clock oscillator. The individual clocks that are generated must operate in a known relationship to each other. In general, these clocks are desirably operated in precise phase with one another. This is typically achieved with the use of phase lock loops (PLLs) and delay lock loops (DLLs). PLLs are very effective in synchronizing clocks to one another, and DLLs are also used for this purpose. Sometimes different elements of the system have different interfaces and are operating at different frequencies. When this is the case, it is necessary that there be two locking mechanisms. One would be a normal PLL which is analog, and the other would be a DLL. The reason for using a DLL instead of two PLLs is that the transfer functions of two PLLs would be very similar to each other and could result in the two resonating together. A DLL has a substantially different transfer function than a PLL so that the likelihood of them resonating can be completely discounted.
One of the problems with DLLs is that there is necessarily a variable delay included in the DLL and the magnitude of that variable delay is advantageously large for functional reasons, but disadvantageously large because it then requires more space on the integrated circuit die. Thus there is a trade-off between functionality and efficient use of space on the integrated circuit die. For a reasonable sized delay, there are two major problems that have existed. One is that lock of the two clocks being synchronized may occur when the amount of delay is very close to zero or very close to the maximum amount of delay. In such a case, a slight change can cause the delay to switch between the maximum and the minimum delay. The reason for this is that there is a counter which controls the amount of delay which counts from all zeros to all ones. When this counter is incremented from the all ones state it will cycle around to the all zeros state. Similarly if the counter is in the all zeros condition and is decremented, it will cycle to the all ones state. If the counter, in the lock condition, is near or at all ones, a small increase will force it to the all zeros condition. This will result in going from a maximum delay to the minimum delay and thus losing lock. Similarly, if it's at near zero in delay so that the counter is at near all zeros and there needs to be a reduction in the amount of delay to retain lock, the counter can go from all zeros to all ones, in which case it goes from the minimum delay to the maximum delay again causing the loss of lock.
Another problem is that if the amount of delay provided in the DLL is not large enough, then it may not be possible to obtain lock if the system is not designed with this in mind. The margin for error in being able to obtain lock may not be adequate. There may be designs that are perfectly reasonable for a circuit board for other criteria, but which will result in requiring an amount of delay not available and thus not attaining lock. Although systems can nearly always be designed so as to require less delay, those kinds of re-designs may not be the kind that a customer or user would want to do. These things can cause delays in bringing a product to market, there may be large re-design costs, or it may be an issue of allocation of resources that is not available or is very costly to the user.
Thus, there is a need for a DLL which can attain lock for a wide range of delay requirements and can avoid attaining lock at the counter boundaries. Shown in FIG. 1 is a system using a DLL according to the prior art which has the two shortcomings described above. Shown in FIG. 1 is a system 10 comprising a PLL 12, a divider 14 shown as VCO CLK divider 14, a divider 16 shown as G clock (GCLK) divider 16, a delay line 18, a counter 20, a phase detector 22, a buffer 24, a buffer 26, a buffer 28, an output pad 30, an output pad 32, an output pad 34, an input pad 36, a delay matched circuit 40, connections 42 and 44, an external circuit 46, and an external circuit 48. Typically, except for delay matched circuit 40, external pads 42 and 44, and external circuits 46 and 48, system 10 would be a single integrated circuit which would have many other elements, such as an ALU, included. Delay line 18, counter 20, and phase detector 22 are typical elements of a DLL. For functionality, of course, there must a source for two clocks, such as PLL 12, VCO CLK divider 14, and GCLK divider 16 coming into the DLL
In operation PLL 12 receives an input system clock (SYSCLK) and provides two clock outputs. One clock operates at twice the frequency of the other. The one operating at the higher frequency is VCO CLK and the one operating at the lower frequency is GCLK. Divider 14 divides VCO CLK by an integer which is at least 2, and divider 16 divides GCLK by half of what divider 14 performs its division by. Divider 14 provides, as an output, a source clock to delay line 18. Divider 16 provides a reference clock to phase detector 22. The source clock must have a 50% duty cycle. The reference clock does not have the same requirement. Delay line 18 receives an input from counter 20 and, based on the output of counter 20, provides delayed source clock to output buffers 24, 26, and 28 which are phased delayed in relation the source clock. Output buffers 24, 26, 28 provide clock out 1, clock out 2, and clock out 3, respectively, on output pads 30, 32, and 34, respectively, in response to the delayed clock. Delay matched circuit 40 is coupled to output pads 30, 32, and 34; to external pads 42 and 44; and to input pad 36. External pads 42 and 44 receive clock out 1 and clock out 2 for use by external circuits 48 and 46 via delayed match circuit 40. Delayed match circuit 40 is also coupled to output pad 34 which carries clock out 3 to input pad 36. Delayed match circuit 40 is for the purpose of, as best as is reasonably possible, matching delays so that the delay between pad 30 and 42, the delay between 32 and 44, and the delay between 34 and 36 are the same. Phase detector 22 receives a feedback clock from pad 36 and the reference clock from divider 16.
In operation phase detector 22 compares the phase relationship of these two clocks and provides an output U/D (up/down) to counter 20. Phase detector 22 provides a clock output to counter 20 to inform the counter if it is to be changed and at the precise time for that change to occur. One technique is to make a determination every five clock cycles. Thus, if changes are needed, a change will only occur on every fifth clock cycle. The U/D signal indicates to the counter if it is to be incremented or decremented and the clock output provides the timing for such increment or decrement. The magnitude of the counter change is limited to an increment or decrement of one for any given occurrence of the clock output. Counter 20 provides an output to delay line 18 which selects the magnitude of the delay. Source clock is delayed to provide the delayed source clock by the amount of delay selected by counter 20. For the case when the feedback clock is leading reference clock, the counter is incremented to increase the amount of delay. When the feedback clock is lagging the reference clock, counter 20 is decremented to reduce the amount of delay in delay line 18. When the feedback clock and the reference clock are in phase, phase generator 22 does not provide the output clock to counter 20.
With this configuration, if delay line 18 has an available delay less than the period of the source clock, there can be the two major problems previously described. One of the problems is that there may not be enough delay available in delay line 18 in order to attain lock at all. In such a case, the user needs to increase the amount of delay in delay matched circuit 40 or elsewhere in order to add sufficient delays so as to obtain lock. If the amount of delay is in the nanosecond range, this could be very space consuming and space which may not be available on the delay match circuit board. For example, a nanosecond of delay on a circuit board using wire only is approximately 20 centimeters. If there are several nanoseconds required, this could be in the range of a third of a meter or even more of wire required to obtain the necessary delay. The other problem is that if lock occurs at the counter boundary or if the lock occurs when the counter is at near all zeros or near all ones, there is very little flexibility left if there is a change in the delay which must be matched by delay 18. The change in delay occurs through temperature changes which could effect the delay in match circuit 40 and buffers 24, 26, and 28. These kinds of changes occur due to temperature changes which are inevitable. When these temperature changes do occur, there is consequent change in delay. The counter may have to increment up when it is already in the all ones condition. In such a condition, it will roll over to all zeros so the delay line 18 provides no delay when it was previously providing maximum delay and more delay was needed. This will result in the loss of lock. Similarly, if the counter is at all zeros, and must be decremented, it will decrement to all ones and delay line 18 will then instead of providing the minimum delay, provide the maximum delay, again causing the loss of lock.